Once a newly designed integrated circuit has been formed on a semiconductor substrate, the integrated circuit must be thoroughly tested to ensure that the circuit performs as designed. Portions of the integrated circuit that do not function properly are identified so that they can be corrected by modifying the design of the integrated circuit. This process of testing an integrated circuit to identify problems with its design is known as debugging. After debugging the integrated circuit and correcting any problems with its design, the final fully functional integrated circuit designs are used to mass produce the integrated circuits in a manufacturing environment for consumer use.
During the debugging process, it is sometimes necessary to probe certain internal electrical nodes in the integrated circuit in order to obtain important electrical data from the integrated circuit, such as for example voltage levels, timing information, current levels, thermal information or the like. The typical integrated circuit device contains multiple layers of metal interconnects. The metal interconnects in the first layer of an integrated circuit device generally carry the most valuable electrical data for debugging purposes. Metal interconnect lines in the first metal layer reside closest to the semiconductor substrate and are usually directly coupled to important components of the integrated circuit device such as for example transistors, resistors and capacitors. It is the electrical data received, manipulated and transmitted by these components that a designer is most interested in analyzing during the debugging process.
FIG. 1A is an illustration of an integrated circuit package 101 that includes wire bonds 103 disposed along the periphery of integrated circuit die 105 to electrically connect integrated circuit connections through metal interconnects 113 to pins 107 of package substrate 111. As shown in FIG. 1A, metal interconnects 113 are coupled to diffusion regions 117 through metal contacts 109. In some instances, diffusion regions 117 may be used in integrated circuit devices such as transistors, resistors, capacitors or the like. As shown in FIG. 1A, a probe tool 115 may be used to probe metal interconnect 113 through the top side 119 of integrated circuit die 105 to obtain the electrical data from integrated circuit die 105.
There are several disadvantages with the wire bond design of integrated circuit package 101 of FIG. 1A. One problem stems from the fact that as the density and complexity of integrated circuit die 105 increases, so must the number of wire bonds 103 required to control the functions integrated circuit die 105. However, there are only a finite number of wire bonds 103 that can fit along the periphery of integrated circuit die 105. One way to fit more wire bonds 103 along the periphery of integrated circuit die 105 is to increase the overall size of integrated circuit die 105, thereby increasing its peripheral area. Unfortunately, an increase in the overall size of integrated circuit die 105 also significantly increases the integrated circuit manufacturing costs.
Another disadvantage with integrated circuit package 101 of FIG. 1A is that the active circuitry within integrated circuit die 105 must be routed through electrical interconnects 113 to the peripheral region of integrated circuit die 105 in order to electrically couple the active circuitry to wire bonds 103. By routing these metal interconnect lines 113 over a relatively long distance across the integrated circuit die 105, the increased resistive, capacitive and inductive effects of these lengthy interconnects 113 result in an overall speed reduction of the integrated circuit. In addition, the inductance of wire bonds 103 may also severely limit high frequency operation of integrated circuit devices in integrated circuit package 101.
With continuing efforts in the integrated circuit industry to increase integrated circuit speeds as well device densities, there is a trend towards using flip-chip technology when packaging complex high speed integrated circuits. Flip-chip technology is also known as control collapse chip connection (C4) packaging. In flip-chip packaging technology, the integrated circuit die is flipped upside-down. This is opposite to how integrated circuits are packaged today using wire bond technology, as illustrated in FIG. 1A. By flipping the integrated circuit die upside-down, ball bonds may be used to provide direct electrical connections from the bond pads directly to the pins of a flip-chip package.
To illustrate, FIG. 1B shows a flip-chip package 151 with an integrated circuit die 155 flipped upside-down relative to the wire bonded integrated circuit die 105 of FIG. 1A. In comparison with wire bonds 103 of FIG. 1A, ball bonds 153 of flip-chip package 151 provide more direct connections between the circuitry integrated circuit die 155 and the pins 157 of package substrate 161 through metal interconnects 159. As a result, the inductance problems that plague typical wire bond integrated circuit packaging technologies are reduced. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die 155, flip-chip technology allows connections to be placed anywhere on the integrated circuit die surface. This results in reduced inductance power distribution to the integrated circuit, which is another major advantage of flip-chip technology.
One consequence of integrated circuit die 155 being flipped upside-down in flip-chip package 151 is that access to the internal nodes of integrated circuit die 155 for debugging purposes has become a considerable challenge. As discussed above, the present day debug process for wire bond technology is based in part on directly probing the metal interconnects through the front side of the integrated circuit die. However, with flip-chip packaging technology, this front side methodology is not feasible since the integrated circuit die is flipped upside-down. For example, as illustrated in FIG. 1B, access to the metal interconnects 159 for the purpose of conventional probing is obstructed by the package substrate 161. Instead, the P-N junctions forming diffusion regions 163 of the integrated circuit are accessible through the back side 165 of the semiconductor substrate of integrated circuit die 155.
FIG. 2 is an example schematic of an integrated circuit 201 that includes a circuit 203 having inputs 205 and 207, and an output 209. As shown in FIG. 2, input 205 is generated by circuit 211 and input 207 is generated by circuit 213. It is appreciated that the example schematic illustrated in FIG. 2 is only one of a countless number of different integrated circuit combinations which may be included in an integrated circuit die.
Assuming a circuit designer wishes to debug integrated circuit 201, it may be desirable to probe signals from inputs 205 and 207, and from output 209. Assume further that the metal interconnects associated with input 205, input 207 and output 209 of FIG. 2 correspond to metal interconnects 159 of FIG. 1B. In this illustration, access to metal interconnects 159 is limited because metal interconnects 159 are obstructed by diffusion regions 163. As a result, the circuit designer would be unable to probe metal interconnects using prior art techniques.
In some instances, it is also not possible to probe input 205, input 207 and output 209 of FIG. 2 through diffusion regions 163 of FIG. 1B. In particular, if diffusion regions 163 are active forward biased transistor diffusions, milling through the semiconductor substrate of integrated circuit die 155 through the back side 165 to expose one of the diffusion regions 163 for probing purposes would damage the forward biased P-N junction. In addition, the lateral spacing between diffusion regions 163 is often insufficient to make feasible the milling away of semiconductor substrate of integrated circuit die 155 from the back side 165 for probing purposes. For instance, diffusion regions 163 are often so closely spaced such that the exposure of a particular diffusion region 163 by milling would often result in the unwanted destruction of nearby structures and/or diffusion regions.
Referring back to FIG. 2, it is also noted that an electrostatic discharge (ESD) protection diode 217 is coupled between input 207 and ground. As is well known in the art, ESD protection diodes such as diode 217 are sometimes coupled to the input gates of transistors in situations where there is not a nearby diffusion region to provide a short ESD path to ground from a transistor gate. To illustrate, the diffusion regions (not shown) of the transistors of circuit 211 provide a nearby ESD path to ground from the gate of the transistor at input 205. Thus, an ESD protection diode is not placed at input 205. In contrast, the diffusion regions (not shown) of circuit 213 are relatively far from the input gates coupled to input 207, thereby resulting in a high metal-to-diffusion ratio associated with input 207. As such, ESD protection diode 217 is placed between input 207 and ground to help protect the gates coupled to input 207 from an ESD event. Note that there is no ESD protection diode coupled to output 209 since there is no input gate at output 209 that needs to be protected from an ESD event.
In sum, ESD protection diodes such as diode 217 are in general only placed on integrated circuit inputs that have a relatively high metal-to-diffusion ratio. ESD protection diodes are generally not placed on integrated circuit outputs nor on integrated circuit inputs with relatively low metal-to-diffusion ratios in the prior art.
In view of the foregoing, what is desired is an improved method and apparatus for probing integrated circuits. Such a method and apparatus should enable the probing of signals through the back side of modern day flip-chip packaged integrated circuits. In addition, such a method and apparatus should allow the probing of both input and output signals of integrated circuits.